Semiconductor memory device and its test method as well as test circuit

ABSTRACT

The present invention provides a semiconductor memory device capable of checking operation in the worst case in address combinations, and its manufacturing method. Specific data for test are written into a memory cell array  30.  Then, a test signal TE 1  is set “1” to set a device in a test mode. Refresh addresses for test are then stored in a data store circuit  51.  A first address for test is applied to an address terminal  21,  whereby a normal read or write operation is accomplished based on the first address for test. A second address for test is applied to the address terminal  21 , whereby a refresh operation is accomplished based on the address for test, and subsequently another normal read or write operation is accomplished based on the second address for test. Data of the memory cell array  30  are checked to decide the presence or absence of any abnormality.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor memory device, and itstest method as well as a test circuit integrated in the semiconductormemory device.

2. Prior Art

It is necessary for the semiconductor memory device to make a variety oftest before shipment, for which purpose in may cases, a test circuit haspreviously been provided in the semiconductor memory device.

FIG. 1 is a block diagram of a semiconductor memory device with such atest circuit, for example, one structural example of a pseudo SRAM (apseudo static random access memory). The structure of this conventionalsemiconductor memory device is disclosed in Japanese Laid-open PatentPublication No. 1-125796. This semiconductor memory device has thefollowing structure.

A memory array 1 has a plurality of memory cells which store data. Asense amplifier 2 is connected to the memory cell array 1 for amplifyingdata from the memory array 1. A column I/O circuit 3 becomes connectedto a bit line of the memory cells in the memory array 1 for selectivelyactivating this bit line. A column decoder 4 receives an input ofexternal addresses A8–A15 and is connected to the column I/O circuit 3,so that the external addresses A8–A15 enter into the column I/O circuit3, whereby the column I/O circuit 3 selectively activates a bit linebased on these external addresses A8–A15. Further, a mainamplifier/write buffer 5 is provided for writing or reading data

A multiplexer 8 is connected to an output side of a refresh controlcircuit 12 and also connected to an output side of an address counter 9,so that in accordance with an output signal from a refresh controlcircuit 12, the multiplexer 8 selects any of externally entered externaladdresses A0–A7 and the refresh address outputted from the addresscounter 9. An output side of the multiplexer 8 is connected to a rowdecoder 7 so that selected one of the external addresses A0–A7 or therefresh address is inputted into the row decoder 7. The row decoder 7 isconnected to a word driver 6 so that any one of the external addressesA0–A7 or the refresh address is inputted into the word driver 6. Theword driver 6 is connected to a word line of the memory cell in thememory array 1, so that the word driver 6 selectively activates the wordline based on the external addresses A0–A7 or the refresh address.

A test mode deciding circuit 10 receives an input of a /CE signal (/representing a negative logic signal) or a /RFSH signal, so that thetest mode deciding circuit 10 decides whether the mode is a test mode ornot, and outputs a test signal which indicates the decided result. Anoutput control circuit 14 is connected to an output side of the testmode deciding circuit 10, so that the output control circuit 14 iscontrolled by the test signal outputted from the test mode decidingcircuit 1 and outputs an I/O output switching signal. Further, theoutput control circuit 14 is connected to the timer circuit 11 and theI/O output switching circuit 15, so that for test, the output controlcircuit 14 controls the I/O output switching circuit 15, whereby afrequency divided signal outputted from the timer circuit 11 is suppliedthrough the I/O output switching circuit 15 to an I/O terminal.

The refresh control circuit 12 receives inputs of the /CE signal and the/RFSH signal, so that if those signals satisfy predetermined conditions,then the refresh control circuit 12 performs refresh operations of thememory cells. The above-described timer circuit 11 outputs a refreshrequest signal periodically at a constant time interval. The timercircuit 11 is connected to the refresh control circuit 12 so that therefresh request signal is inputted into the refresh control circuit 12.A timing generating circuit 13 is connected to this refresh controlcircuit 12 for receiving an input of the refresh control signaloutputted from the refresh control circuit 12 and also receives externalinputs of an /RE signal, an /OE signal and a CS signal, so that thetiming generating circuit 13 outputs an internal synchronizing signaland controls operations of the entirety of the circuit.

In such configurations, if the /RFSH signal is a low level (L) at a timewhen the /CE signal is transited from a high level (H) to a low level(L), then the test mode deciding circuit 10 decides that the mode is thetest mode. In this case, the test mode deciding circuit 10 transmits asignal through the output control circuit 14 and outputs this signal foroscillating the timer circuit 11, whereby the refresh control circuit 12operates the address counter 9 and controls the multiplexer 8, so thatthe refresh address (n-address) of the address counter 9 is outputtedfrom the multiplexer 8 as the row address of the memory cells. Theexternal addresses A8˜A15 are entered as the column addresses to thecolumn decoder 4.

In the above manners, a memory cell of a designated address by the rowaddress of n-address and the column addresses A8˜A15, so that a read outoperation of data content of the cell is accomplished. Accordingly, thespecific data have previously been written into the cell of this addressso that in the test mode, the content in the cell is directly read out,thereby accurately deciding whether or not data have correctly beenwritten and read out. Namely, it is possible to accurately decidewhether or not the timer circuit 11 and the address counter 9 normallyoperate.

When the mode is set into the test mode, the timer circuit 11 isoscillated, wherein the frequency divided signal outputted from thetimer 11 is supplied through the output switching circuit 15 to the I/O7terminal. Checking the frequency divided output signal results in anaccurate decision on whether or the timer circuit 11 normally operates.

Issue to be Solved by the Invention

The above described pseudo SRAM is a semiconductor memory device whichhas the same memory cell structure as the DRAM (dynamic random accessmemory), and has the same condition in use as the SRAM, wherein it isnecessary to internally perform a self-refresh of the memory cells everywhen a predetermined time passes.

The address of the memory cell to be self-refreshed or the refreshaddress is generated by the inside of the circuit, for which reason therefresh address is completely irrelevant to the externally suppleidread/write addresses.

In the worst case, for example, it is possible that adjacent two of theword lines are sequentially activated, wherein the common bit line isactivated. In this case, it is possible that any memory malfunctionappears due to an insufficient pre-charge and a slight leakage ofcurrent under a field insulating film.

The test conducted by the above-described semiconductor memory deviceis, however, only to check the operations of the timer circuit 11 andalso sequentially read out the data of the memory cells by sequentiallychanging the counted value of the address counter 9. It is impossible tointentionally check the operations or make the test in the worst casewhich is likely to cause the above-described malfunction.

In consideration of the above-described circumstances, an object of thepresent invention is to provide a semiconductor memory device which iscapable of checking operations under any conditions.

A further object of the present invention is to provide a test circuitintegrated in a semiconductor memory device and capable of checkingoperations under any conditions.

A furthermore object of the present invention is to provide a testmethod capable of checking operations a semiconductor memory deviceunder any conditions.

Means for Solving the Issue

The present invention was made to solve the above-issues, and provides atest method for a semiconductor memory device with a plurality of memorycells which need refreshes, wherein during a test operation, there isaccomplished, at least one time, a combination of: a read/write processfor reading or writing the memory cell based on a first addressexternally entered; and a refresh process for refreshing the memorycells based on a second address externally entered.

The combination of two processes may optionally be that after therefresh process is made, then the read/write process is made.

The combination of two processes may optionally be that after theread/write process is made, then the refresh process is made.

The combination of two processes may optionally be made in one cycle.

The read/write process and subsequent the refresh process and furthersubsequent the read/write process may optionally be accomplished in onecycle.

The two processes may optionally be made at a common column address andat row addresses close to each other.

The two processes may optionally be made at a common column address andat row addresses adjacent to each other.

The test method for a semiconductor memory device may optionally furtherinclude a process of discontinuing the refresh of the memory cell basedon a third address generated inside of the semiconductor memory device,in response to a switch of the semiconductor memory device from a normaloperation mode to a test mode.

When the normal operation mode is switched to the test mode based on amode switching signal externally entered, the test address may beselected from the third address and the test address, so that therefresh of the memory cell based on the third address may bediscontinued.

The semiconductor memory device may optionally be switched from thenormal operation mode to the test mode based on a mode switching signalexternally entered.

When the normal operation mode may be switched to the test mode based onthe mode switching signal externally entered, the test address may beselected from the third address and the test address, so that therefresh of the memory cell based on the third address may bediscontinued.

The test operation may optionally be that a set of plural row addressesis subject to the refresh operation with fixing a column address andsequentially changing row addresses.

The test operation may optionally be that a set of all row addresses issubject to the refresh operation with fixing a column address andsequentially changing row addresses.

The test operation may optionally be that a set of respective all rowaddresses for each of plural blocks divided from a memory cell array issubject to the refresh operation with fixing a column address andsequentially changing row addresses.

Both the first address and the second address may optionally beexternally entered every changes of the row address.

The first address may optionally be externally entered every changes ofthe row address, while only an initial address of the second address isexternally entered, and the second address may be automatically changedin accordance with a predetermined constant rule every changes to therow address.

A predetermined increment of the second address may optionally be madeevery changes to the row address.

A hold test of a memory cell to be subject to the test may be previouslytested and a predetermined test pattern may be written, before the twoprocesses may be accomplished.

The present invention provides a semiconductor memory device having aplurality of memory cells which need refresh, a circuit element forsupplying a first address, and an access address control circuit forrefreshing the memory cell based on an address, wherein thesemiconductor memory device further has: a circuit for holding a secondaddress externally entered; and a refresh address switching circuitelectrically coupled to the circuit element for supplying the firstaddress and also coupled to the circuit for holding the second address,and in a normal operation mode, the refresh address switching circuitsupplies the first address to the access address control circuit, and ina test mode, the refresh address switching circuit supplies the secondaddress to the access address control circuit.

The refresh address switching circuit may optionally comprise aselecting circuit which is electrically coupled to the circuit elementfor supplying the first address and also coupled to the circuit forholding data, and in the normal operation mode, the selecting circuitselects the first address, and in the test mode, the selecting circuitselects the second address.

The selecting circuit may optionally comprise a multiplexer electricallycoupled to the circuit element for supplying the first address and alsocoupled to the circuit for holding data.

The semiconductor memory device may optionally further include: acontrol circuit electrically coupled to the refresh address switchingcircuit for supplying the refresh address switching circuit a controlsignal which switches between the normal operation mode and the testmode.

The control circuit may optionally comprise a test entry circuit whichswitches between the normal operation mode and the test mode in responseto a predetermined external signal.

The circuit for holding the second address may optionally comprise adata storage device electrically coupled to the refresh addressswitching circuit.

The semiconductor memory device may optionally further include anaddress inverting circuit electrically coupled to between the circuitfor holding data and the refresh address switching circuit for invertingthe second address outputted from the data storage device, and supplyingthe same to the refresh address switching circuit.

The circuit element for supplying the first address may optionallycomprise a refresh address generating circuit connected to the refreshaddress switching circuit.

The present invention provides a test circuit for a semiconductor memorydevice, the circuit having a plurality of memory cells which needrefresh and a circuit element for supplying a first address based on aninternal signal, wherein the test circuit has: a circuit for holding asecond address externally entered; and a refresh address switchingcircuit electrically coupled to the circuit element for supplying thefirst address and also coupled to the circuit for holding the secondaddress, and in a normal operation mode, the test circuit supplies thefirst address to the access address control circuit, and in a test mode,the test circuit supplies the second address to the access addresscontrol circuit.

The refresh address switching circuit may optionally comprise aselecting circuit which is electrically coupled to the circuit elementfor supplying the first address and also coupled to the circuit forholding data, and in the normal operation mode, the selecting circuitselects the first address, and in the test mode, the selecting circuitselects the second address.

The selecting circuit may optionally comprise a multiplexer electricallycoupled to the circuit element for supplying the first address and alsocoupled to the circuit for holding data.

The test circuit may optionally further include: a control circuitelectrically coupled to the refresh address switching circuit forsupplying the refresh address switching circuit a control signal whichswitches between the normal operation mode and the test mode.

The control circuit may optionally comprise a test entry circuit whichswitches between the normal operation mode and the test mode in responseto a predetermined external signal.

The circuit for holding the second address may optionally comprise adata storage device electrically coupled to the refresh addressswitching circuit.

The test circuit may optionally further include an address invertingcircuit electrically coupled to between the circuit for holding data andthe refresh address switching circuit for inverting the second addressoutputted from the data storage device, and supplying the same to therefresh address switching circuit.

The test circuit may optionally be integrated in the semiconductormemory device, or be separated from the semiconductor memory device andbe mounted on a same chip as the semiconductor memory device. In eitherconfiguration, there is no problem, provided that the test circuit iselectrically coupled to the semiconductor memory device, and signals andaddresses are transmitted between the test circuit and the semiconductormemory device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing the structural example of theconventional semiconductor memory device.

FIG. 2 is a block diagram showing a structure of one embodiment of thisinvention.

FIG. 3 is a timing chart describing a normal operation in theembodiment.

FIG. 4 is a timing chart describing a test operation in the embodiment.

FIG. 5 is a flow chart describing a test operation in the embodiment.

FIG. 6 is another flow chart describing a test operation in theembodiment.

FIG. 7 is a circuit diagram showing one example of a circuitconfiguration of a multiplexer included in the circuit configuration ofFIG. 2.

MODE FOR CARRYING OUT THE INVENTION

One embodiment of the present invention will, hereinafter, be describedwith reference to the drawings. In the following embodiment, onestructural example is shown, wherein the test circuit is integrated inthe semiconductor memory device.

FIG. 2 is a block diagram showing a circuit configuration of asemiconductor memory device (pseudo SRAM) in accordance with thisembodiment. FIG. 3 is a timing chart of output signals from respectivecircuits of the semiconductor memory device shown in FIG. 2. The circuitconfiguration of the semiconductor memory device (pseudo SRAM) will bedescribed with reference to FIG. 2, while the output signals from therespective circuits will be described with reference to FIG. 3. Aread/write address Add is applied to an address terminal 21 fromoutside. A terminal 22 is applied with a first test signal TE1 fromoutside. A terminal 23 is applied with a second test signal TE2 fromoutside. Only the terminal 22 is a terminal dedicated for the test. Theterminal 21 is applied with the read/write address Add in the normaloperation. The terminal 23 is also applied with an output enable signalOE in the normal operation and serves as a terminal for receiving thetest signal.

An address transition detector circuit (ATD circuit) 25 is connected tothe terminal 21 for receiving an input of the read/write address Addwhich was applied to the terminal 21 from outside, so that the addresstransition detector circuit 25 detects any transition of row addressdata AddR (see FIG. 3) included in this address data Add. If at leastone bit in all bits of the row address data AddR is transitioned, thenthe address transition detector circuit (AD circuit) 25 detects thetransition and outputs a pulse signal ATD.

A row control circuit 26 is connected to an output side of the addresstransition detector circuit (ATD circuit) 25, so that, based on thepulse signal ATD outputted from the address transition detector circuit(ATD circuit) 25, the row control circuit 26 generates and outputs a rowenable signal RE, a sense enable signal SE and a column control signalCC. As shown in FIG. 3, the row enable signal RE is a pules signal whichrises at a rising time and a falling time of the pulse signal ATD, andthen falls after a predetermined time passes from those times. The senseenable signal SE is a signal delayed by a predetermined time from therow enable signal RE. Even not shown in the drawing, the column controlsignal CC is a later one of two sequential row enable signals RE, namelya signal delayed by a predetermined time from the pulse signal based onthe falling of the signal ATD. When the second text TE2 is “0” or in thelow level, the row control circuit 26 does not output the row enablesignal RE.

A column control circuit 27 is connected to the row control circuit 26for receiving the column control signal CC outputted from the rowcontrol circuit 26 and further delays the column control signal CC, andoutputs a column enable signal CE.

A memory cell array 30 has a similar structure as a memory cell array ofDRAM. A row decoder 31 is connected to word lines of the memory cellarray 30 and also connected to the row control circuit 26, so that at atiming when the row enable signal RE outputted from the row controlcircuit 26 becomes “1”, the row decoder 31 selectively activates a wordline of the memory cell array 30, wherein the word line corresponds torow address data RA1 outputted from a multiplexer (MUX) 32.

A sense amplifier 33 is connected to each bit line of the memory cellarray 30 and also connected to the row control circuit 26, so that thesense amplifier 33 activates each bit line of the memory cell array 30at a timing when the sense enable signal SE outputted from the rowcontrol circuit 26 becomes “1”.

A column decoder 35 is connected to the above-described terminal 21 andthe column control circuit 27, so that at a timing when a column enablesignal CE outputted from the column control circuit 27 becomes “1”, thecolumn decoder 35 decodes column address data AddC included in theaddress data Add applied to the terminal 21, so that a sense amplifiercorresponding to this decode result is connected through an I/O buffer36 to an input/output data terminal 37.

A refresh control circuit 40 is a circuit for self-refresh of the memorycell array 30. This refresh control circuit 40 is connected to an outputside of the address transmission detector circuit (ATD circuit) 25 forreceiving the pulse signal ATD and outputs a pulse signal and a resetsignal at a time when the pulse signal AID falls. The refresh controlcircuit 40 is further connected to a timer 42 and a refresh addressgenerating circuit 41, so that the refresh control circuit 40 outputs apulse signal at a time when the pulse signal ATD falls, and the pulsesignal as outputted is entered into the refresh address generatingcircuit 41, and the reset signal is entered into the timer 42. Therefresh address generating circuit 41 receives the pulse signal andmakes an increment by one of the refresh address RFAD.

The above-described refresh control circuit 40 detects, based on a timersignal from the timer 40 that any output of the pulse signal ATD fromthe address transition detector circuit (ATD circuit) does not appearfor a predetermined time, so that the refresh control circuit 40 outputsa self-refresh signal RF. An output side of the refresh control circuit40 is connected to the row control circuit 26, so that the self-refreshsignal RF as outputted is entered into the row control circuit 26.

Further, a test circuit 50 for testing a pre-shipment complete productreceives inputs of first and second test signals which were applied tothe terminals 22 and 23, and the test circuit 50 outputs an outputsignal T3 and a refresh address RA. The refresh control circuit 40 isconnected to the test circuit 50 for receiving an input of the outputsignal T3 and then outputting a signal M and a self-refresh signal RF,whereby a self-refresh of the memory cell array 30 is conducted.

The test circuit 50 comprises a data store circuit 51, an invertercircuit 52, a test entry circuit 53 and a multiplexer 54. The data storecircuit 51 captures and outputs row address data AddR included in theaddress data Add which were applied to the terminal 21, at a timing whenthe signal T1 outputted from the text entry circuit 53 rises. The rowaddress data AddR as outputted is entered into the inverter circuit 52.The inverter circuit 52 inverts respective bits outputted from the datastore circuit 51 and outputs a test address TA. The test entry circuit53 is connected to the terminals 22 and 23, and the test entry circuit53 outputs signals T1˜T3 based on the first and second test signals TE1and TE2 which were applied to those terminals. The multiplexer 54selects any one of the test address TA from the inverter circuit 52 andthe refresh address RFAD from the refresh address generating circuit 41,based on the signal T2 from the test entry circuit 53, and themultiplexer 54 outputs a signal RA This signal RA is entered into theabove-described multiplexer 32.

The test mode operation and the normal operation of the above-describedsemiconductor memory device will be described separately.

Initially, the normal operation will be described with reference to FIG.3. In this mode, the test signal TE1 is set at “0”, whereby the signalsT1˜T3 outputted from the test entry circuit 53 become “0”. In the normaloperation, the test circuit 50 does not operate, and thus the operationis substantially the same as the semiconductor integrated circuit freeof any integration of the test circuit.

In this state, when data “A1” as the row address data AddR are appliedto the terminal 21, the ATD circuit 25 detects that the data “A1” wereapplied, whereby the pulse signal ATD (“1”) is entered into the rowcontrol circuit 26 and the multiplexer 32. The multiplexer 32 receivesthe pulse signal ATD (“1 ”) and outputs data RA from the multiplexer 54as the row address data RA1. The row address data RA1 are then enteredinto the row decoder 31.

Since the signal T2 is “0”, the multiplexer 54 outputs the refreshaddress RFAD which is supplied through the multiplexer 32 to the rowdecoder 31, provided that the refresh address RFAD was “R1”.

On the other hand, the row control circuit 26 receives the pulse signalATD and outputs the row enable signal RE. This row enable signal RE isentered into the row decoder 31. The row decoder 31 receives this rowenable signal RE and activates a word line designated by theabove-described address data “R1”.

Subsequently, the row control circuit 26 outputs the sense enable signalSE which is then supplied to the sense amplifier 33, whereby the senseamplifier is activated. After the sense amplifier 33 is activated, amemory cell connected to a word line designated by the above-describedrow address data “R1” is refreshed.

When the pulse signal ATD falls, the refresh control circuit 40 suppliesa pulse signal to the refresh address generating circuit 41, whereby therefresh address RFAD is incremented and becomes “R1+1”. Simultaneously,the timer 42 is reset. When the pulse signal ATD falls, the multiplexer32 supplies the row decoder 31 the data AddR (data “A1” at this time) asthe row address data RA1. When the pulse signal ATD falls, the rowcontrol circuit 26 supplies the row enable signal RE to the row decoder31.

The row decoder 31 receives the row enable signal RE and activates aword line of the memory cell array 30, wherein the word line isdesignated by row address data “A1” outputted from the multiplexer 32.Subsequently, the row control circuit 26 outputs the sense enable signalSE which is then supplied to the sense amplifier 33, whereby a word linecorresponding to the address data “A1” of the sense amplifier 33 isactivated.

Subsequently, the column control circuit 27 supplies the column enablesignal CE to the column decoder 35. The column decoder 35 receives thecolumn enable signal CE and decodes a column address data AddC, so thata sense amplifier corresponding to this decode result is connectedthrough the I/O buffer 36 to the input/output data terminal 37. In caseof read operation, data stored in the memory cell array 30 aretransmitted through the sense amplifier 33 and the I/O buffer 36 to thedata terminal 37. In case of write operation, data on the data terminal37 are written into the memory cell array 30.

As described above, in accordance with the semiconductor memory deviceof FIG. 2, after the read/write address data Add are applied to theaddress terminal 21, a refresh of a memory cell connected to a word linedesignated by the refresh address RFAD is made and subsequently aread/write operation of the memory cell array 30 is made based on theaddress data Add.

If the read/write operation of the memory cell array 30 has not beenconducted within a predetermined time period, then the timer 42 suppliesthe pulse signal to the refresh control circuit 40. The refresh controlcircuit 40 receives the pulse signal and conducts the self-refresh.Namely, the refresh signal RP is supplied to the row control 26, and thesignal M of “1” is supplied to the multiplexer 32. The multiplexer 32receives this signal M and supplies the row decoder 31 the refreshaddress RFAD (data “R1+1 ”) as the row address data RA1.

The refresh signal RF is supplied to the row control circuit 26, andthen the row control circuit 26 supplies the row enable signal RE to therow decoder 31 and subsequently supplies the sense enable signal SE tothe sense amplifier 33, whereby a memory cell connected to a word linecorresponding to the row address data “R1+1” is refreshed similarly tothe above case.

The above descriptions are the normal operations of the semiconductormemory device shown in FIG. 2.

Subsequently, the pre-shipment test operation using the test circuit 50will be described with reference to FIG. 4, which is a timing chart fordescribing the test operation.

A variety of patterns as test patterns for the pre-shipment test may beconsidered. As one example, it is possible to conduct the test, whereina read/write “address B” is “X1”, and “refresh address A” is an invertedaddress “/X1” of “X1”. The following descriptions will be made by takingone example that the read/write “address B” is “X1” and “refresh addressA” is the inverted address “/X1”.

In this pre-shipment test, at a time t1, the test signal TE1 rises up to“1”, whereby the test entry circuit 53 enters into the test mode, andthereafter the test entry circuit 53 recognizes any signals applied tothe terminal 23 to be the second test signal TE2. Subsequently, theaddress data “X1” are applied to the terminal 21. At a time t2, thesecond test signal TE2 applied to the terminal 23 falls to “0”.

The second test signal TE2 falls to “0”, then the test entry circuit 53detects this fall, and rises the signal T1 to “1”. The signal T1 risesto “1”, and upon this rising, the data store circuit 51 captures theaddress data AddR applied to the address terminal 21, namely the addressdata “X1”, whereby the address data “X1” are then supplied to theinverter circuit 52. The inverter circuit 52 inverts the address data“X1” and outputs the same as data “/X1”. The inverted address data “/X1”are supplied as the test address data to the multiplexer 54.

In the above embodiment, as described above, the inverter 52 isinterposed between the data store circuit 51 and the multiplexer 54.Thus, it is possible to conduct the refresh at the inverted address“/X1” and the read/write operation at the address “X1” without anychange to the address data “X1” to be applied to the address terminal21. Namely, in the read or write operation, the multiplexer 32 selectsthe address “X1” which was entered through the address terminal 21 sothat the read or write operation is made at the address “X1”. In therefresh operation, the multiplexer 32 selects the inverted address “/X1”which was entered through the address terminal 21 and inverted by theinverter 52, so that the read or write operation is made at the invertedaddress “/X1”.

The address data “X1” supplied from an external tester may be usedcommonly for both the read or write operation and the refresh operation.This may make it easy to prepare he test patterns and also make a testprogram simple.

In case that the inverter 52 is not provided, it is necessary that theinverted address data “/X1” are applied as the refresh address to theaddress terminal 21. Every when the read or write address is changed,then the inverted address as the refresh address is needed to be appliedto the address terminal 21. As a result, the test program is likely tobe complicated. This is more remarkable as a scale of the memory cellarray is large.

Accordingly, it is preferable to provide the inverter 52 for allowingthe address data applied to the address terminal 21 to be used commonlyfor both the read or write operation and the refresh operation. Theinverter 52 is mere circuit design choice and not essential for the testcircuit. For example, depending upon the test pattern, it is notnecessary that the read or write address B is “X1”, the refresh addressA is the inverted address “/X1” of “X1”. In this case, it is unnecessaryto provide, on purpose, the inverter 52.

At a time t3, the address data “X1” as the read/write address “B” as theaddress data AddR are applied to the address terminal 21. The addressdata “X1” are applied to the address terminal 21, and as describedabove, the pulse signal ATD is outputted from the ATD circuit 25. Theoutputted pulse signal MD is entered into the row control circuit 26.Since at this time, the test signal TE2 is “0”, then the row enablesignal RE and the sense amplifier enable signal SE are not outputtedfrom the row control circuit 26.

The second test signal TE2 rises to “1” at a time t4, that apredetermined time (a time slightly longer than a pulse width of thepulse signal ATD) passes from the time t3 when the address data “X1” wasapplied to the terminal 21. The test signal TE2 rises to “1”, and thenthe test entry circuit 53 detects this rising, and the signals T2 and T3rise to “1”. The signal T2 rises to “1”, then the multiplexer 54 outputsthe test address data TA as the address data RA.

At this time t4, the signal 13 rises, and the refresh control circuit 40detects this rising, and supplies the self-refresh signal RF to the rowcontrol circuit 26 and also supplies the signal M to the multiplexer 32.The signal M is entered into the multiplexer 32, and the multiplexer 32supplies the address data AddR (the data “X1” at this time) to the rowdecoder 31. When the signal RF is entered into the row control circuit26, the second test signal TE2 has already risen to “1”. Thus, the rowenable signal RE is outputted from the row control circuit 26. This rowenable signal RE is then entered into the row decoder 31, whereby a wordline designated by the address data “X1” is activated. Subsequently, thesense enable signal SE is outputted from the row control circuit 26, andthen he sense amplifier 33 is activated, and the read/write is made tothe word line designated by the address data “X1”.

At a time t5, address data “C” are applied to the address terminal 21.When the address data “C” are applied to the address terminal 21, thenthe ATD circuit 25 detects this, and supplies the pulse signal ATD (“1”to the multiplexer 32 and the row control circuit 26. The multiplexer 32selects an output from the multiplexer 54, namely the test address TA(the address data “/X1” as the refresh address A at this time), and thensupplies the selected data to the row decoder 31. As the pulse signal ADis supplied to the row control circuit 26, the second test signal TE2has been “1”, and thus the row enable signal RE is outputted from therow control circuit 26, and the row enable signal RE as outputted isthen entered into the row decoder 31, whereby the word line designatedby the address dara “/X1” is activated. Subsequently, the sense enablesignal SE is outputted from the row control circuit 26, and the senseamplifier 33 is activated, whereby the memory cell connected to the wordline designated by the address data “/X1” is refreshed.

At a time t6, the pulse signal ATD falls to “0”, then the multiplexer 32supplies the address data AddR (data C at this time) to the row decoder31. When the pulse signal ATD falls to “0”, and the row enable signal REis outputted from the row control circuit 26. The row enable signal REas outputted is entered into the row decoder 31, whereby a word linedesignated by the address data “C” is activated. Subsequently, the senseenable signal SE is outputted from the row control circuit 26, and thesense amplifier 33 is activated, and a read/write operation of the wordline designed by the address data “C” is made.

As described above, the test circuit 50 shown in FIG. 2 is capable ofpreviously setting the test-purpose refresh address (the above addressdata “A” in the data store circuit 51. Since the refresh address “A”previously set in the data storage circuit 51 could have been previouslyrecognized, it is possible that the test-purpose read/write addresses(the above-described address data “B”, “C”) adjacent to this refreshaddress are entered from outside, so that the test under any conditions,for example, the worst condition, may intentionally and surely made.

A word line is designated based on the refresh address “A” forrefreshing the memory cell and subsequently an adjacent word line to theabove word line is designated based on the test-purpose read/writeaddress for the read/write operation, so that the test is intentionallymade, wherein adjacent two of the word lines are sequentially activatedwith fixing a common bit line. Namely, it is possible to verify whetheror not any malfunction of the storing operation appears under anyconditions, for example, under the worst condition with an insufficientpre-charge or a slight leakage of current under a field insulating film.

The pre-shipment test using the above-described test circuit 50 will bedescribed with reference to the flow chart of FIG. 5.

If a chip originally has any stationary defect or has a memory cell witha bad hold characteristic, then the test for refresh operation is nosense, for which reason the holding test is needed to be carried outpreviously (Step S1). The holding test may be made in the known testsequences similarly to those of the test taken place for thegeneral-purpose DRAM.

Namely, data are written into memory cells of the memory cell array 30and the refresh remains inhibited for a predetermined time, before dataare read out from the memory cells, wherein the predetermined time (orrefresh cycle) is adjusted so that the read out data correspond to thewritten data, thereby deciding the hold times of the memory cells. Thistest is conducted for all of the memory cells, so that it is possible todecide the refresh cycle based on the shortest hold time of the memorycells. The inhibition of the refresh operation may be made by entry ofthe control signal into the refresh control circuit 40.

Subsequently, in order to make a post-test decision on whether or notthe refresh operation and the read/write operation are made correctly,the test patterns have previously been written into the memory cellarray 30 (Step S2). In order to investigate the normality of the refreshoperation and the read/write operation, the test pattern with all bitsof “1” is used.

An optional hold time is set (Step S3). Subsequently, the first testsignal TE1 is risen to “1” to set the circuit into the test mode (StepS4).

Subsequently, the refresh address data (“A”) are applied to the addressterminal 21, to cause the test signal TE2 to be fallen to “0”, wherebythe address data “A” are written into the data store circuit 51 (StepS5).

Address data (“B”) are applied to the address terminal 21, wherein theaddress data (“B”) designate a word line which is connected to the samesense amplifier as a word line which is designated by the address data“A” (Step S6).

After the predetermined time has passed, similarly to the above, Addressdata (“C”) are applied to the address terminal 21, wherein the addressdata (“C”) designate a word line which is connected to the same senseamplifier as a word line which is designated by the address data “A”(Step S7).

Through the above processes, as shown in FIG. 4, the normal access tothe address “B”, the refresh operation at the address “A” and the normalaccess to the address “C” are sequentially conducted.

Subsequently, data stored in the memory cells connected to therespective word lines designated by the above addresses “A”, “B” and “C”are read out and then checked (Step S8). If the result of the check is“NG” (Step S9), then the test is finished and the chip is disposed (StepS10). If the result of the check is “PASS” (Step S9), then it is decidedwhether or not the entirety of the test has been completed (Step S11).If the result of the decision is “NO”, then it returns to the step S5.

Thereafter, the above steps S5˜S8 are repeated until the result ofdecision on, whether or not the entirety of the test has been completed,becomes “YES”. The test is made for all combinations of the rowaddresses with the common sense amplifier. For testing the allcombinations of the row addresses, it is possible that a word line isfixed as a refresh word line, while the word lines of the normalaccesses before and after the refresh operation are sequentiallychanged. For example, a word line is fixed as a refresh word line, whilethe word lines of the normal accesses before and after the refreshoperation are sequentially changed from the top one to the bottom one.

The above test process will be repeated by fixing another word line asthe refresh word line until all of the word lines have been selected asthe refresh word line, whereby the test is made for all of the testpatterns.

In case that the memory cell array 30 is divided into a plurality ofblocks, each of which is allocated with each sense amplifier, the testmay be made for all combinations of the row addresses in the each block.

Practically, it take a long time to make the test for all patterns. Itis possible alternatively to make the test with disciplined addresses.Namely, initially, all patterns are subject to the test, but after anytendency appears, some of the patterns may be omitted. For the testtechniques for not only the DRAM but also the normal memory, there maybe a pattern which is likely to find out the defects. For example, acombined test of test methods such as mating or gallop may be effective.Needless to say, it is preferable to conduct the test for all patterns.

In the above-described embodiment, the test is made by changing the rowaddress, independently from the column addresses. In the normalaccesses, the bit line is connected through a column switch to a databus. The data of the memory cells may be influenced depending on how toopen the bit lines and pre-charge. Accordingly, it is preferable toconduct the test with further changing the column addresses.

In this case, it is possible to add a process for setting optionalcolumn address data AddC following to the step S5 in FIG. 5. FIG. 6 is aflow chart of the test to be conducted by changing not only the rowaddresses but also the column addresses.

The steps S1˜S5 are conducted similarly to the above. Thereafter, data“D” as the column address data AddC are applied to the address terminal21. The column decoder 35 decodes the column address data AddC, and asense amplifier corresponding to the decoded result is connected throughthe I/O buffer 36 to the input/output data terminal 37. Namely, the bitline is designated by the column address data AddC (Step S12). Addressdata (“B”) are applied to the address terminal 21, wherein the addressdata (“B”) designate a word line which is connected to the same senseamplifier as a word line which is designated by the address data “A”(Step S6).

After the predetermined time has passed, similarly to the above, Addressdata (“C”) are applied to the address terminal 21, wherein the addressdata (“C”) designate a word line which is connected to the same senseamplifier as a word line which is designated by the address data “A”(Step S7).

Through the above processes, the normal access to the address “B”, therefresh operation at the address “A” and the normal access to theaddress “C” are sequentially conducted with fixing a bit line designatedby the column address AddC.

The same test will be repeated by changing the bit lines designated. Inaddition to the refresh row address, the column address is also changedfor the test in order to investigate whether or not the data of thememory cells may be influenced depending on how to open the bit linesand pre-charge.

In accordance with the above embodiment, enabling to optionally set theaddress from the outside of the chip increases the flexibility. In otherwords, designation of all of the addresses should be made from theoutside. This is complicated and inconvenience method. It is, however,possible that the above normal access addresses “B” and “C” only aregiven from the outside, while the refresh address “A” is automaticallyincremented inside of the circuit, so as to save the programming workfor the test program. In this case, it is possible to increment therefresh address by utilizing the address counter in the refresh addressgenerating circuit 41.

In case that the test-purpose refresh address (the above address data“A”) is automatically incremented inside of the test circuit 50, theincrement is made in accordance with the predetermined rule, for whichreason it is possible to previously recognize the incremented refreshaddress (address data “A+1”). Thus, it is possible that the test-purposeread/write addresses (the above-described address data “B”, “C”)adjacent to this incremented refresh address are entered from outside,so that the test under any conditions, for example, the worst condition,may intentionally and surely made.

Namely, the word line is designated by the automatically incrementedrefresh address for taking place the refresh operation of the memorycell, and subsequently the word lines adjacent to the above word lineare designated by the test-purpose read/write address for taking placethe read/write operation, thereby enabling the test under any optionalconditions, for example, the worst condition without designating all ofthe addresses from the outside.

In the above embodiment, the multiplexer 54 receives the refresh addressRFAD outputted from the refresh address generating circuit 41 and alsoreceives the test address TA outputted from the data store circuit 51,and, in the normal operation mode, the multiplexer 54 selects therefresh address RFAD generated in the circuit based on the controlsignal T2 from the test entry circuit 53, and in the test mode, themultiplexer 54 selects the test address TA entered from the outside. Inresponse to the change from the normal operation mode to the test mode,the supply of the refresh address RFAD generated inside of the circuitis discontinued, so that in the test mode, it is prevented that therefresh operation is made based on the refresh address RFAD generatedinside of the circuit.

One example of. the circuit configuration of the above-describedmultiplexer 54 is shown in FIG. 7. The multiplexer 54 has a first gatefurther comprising a first n-type transistor N1 and a first p-typetransistor P1, a second gate further comprising a second n-typetransistor N2 and a second p-type transistor P2, and an inverter INV1.The multiplexer 54 also has a test address input unit for the testaddress TA which was outputted from the data store circuit 51 andentered through the inverter 52, and a refresh address input unit forreceiving an input of the refresh address RFAD outputted from therefresh address generating circuit 41, a control signal input unit forreceiving an input of the signal T2 outputted from the test entrycircuit 53, and an output unit of the circuit.

The first gate comprising he first n-type transistor N1 and the firstp-type transistor P1 is provided between the test address input unit andthe output unit. The second gate comprising the second n-type transistorN2 and the second p-type transistor P2 is provided between the refreshaddress input unit and the output unit.

Further, the control signal input unit is connected to a gate of thefirst n-type transistor N1, a gate of the second p-type transistor P2,and an input side of the inverter INV1. An output side of the inverterINV1 is connected to a gate of the first p-type transistor P1 and a gateof the second n-type transistor N2.

The signal 12 outputted from the test entry circuit 53 is entered intothe gate of the first n-type transistor N1 and the gate of the secondp-type transistor P2, while the inverted signal of the signal T2 isentered into the gate of the first p-type transistor P1 and the gate ofthe second n-type transistor N2.

Accordingly, in the normal operation mode, the signal T2 is in theinactive state or in the low level “L”, whereby the first gatecomprising the first n-type transistor N1 and the first p-typetransistor P1 is closed, while the second gate comprising the secondn-type transistor N2 and the second p-type transistor P2 is opened. Thetest address TA is not outputted, while the refresh address RFAD isoutputted, so that the refresh operation is made of the memory cellbased on the refresh address RFAD generated inside of the circuit in thenormal operation mode.

In the test mode, the signal T2 is in the active state or in the highlevel “H”, whereby the first gate comprising the first n-type transistorN1 and the first p-type transistor P1 is opened, while the second gatecomprising the second n-type transistor N2 and the second p-typetransistor P2 is closed. The test address TA is outputted, while therefresh address RFAD is not outputted, so that the refresh operation ismade under the worst condition of the memory cell based on the testaddress TA entered from the outside of the circuit in the test mode. Theabove-multiplexer 54 is mere one example of the circuits which have afunction of selecting any one of the test address TA and the refreshaddress RFAD based on the control signal generated upon transitionbetween the normal operation mode and the test mode. It is notunnecessary to limit the circuit to this multiplexer. It is no problem,provided that the row address for access for the read/write operation inthe test mode and the row address for access for the refresh operationare surely controllable from the outside.

In the above embodiment, there was described one case that after therefresh operation is made, then the read/write operation is made. Thepresent invention is also applicable to another case that after theread/write operation is made, then the refresh operation is made.

As described above, the test-purpose refresh address (the above addressdata “A”) may previously be set in the data store circuit 51 and therefresh address “A” may previously be recognized, for which reason it ispossible that the test-purpose read/write addresses (the above addressdata “B” and “C” are entered from the outside of the circuit, so thatword lines adjacent to the word line designated by the refresh address“A” are designated based on the test-purpose read/write addresses fortaking place the test-purpose read/write operations, and subsequentlythe word line is designated by the refresh address “A” for taking placethe refresh operation of the memory cell. This allows that the test isintentionally and surely made under the worst conditions, whereinadjacent two of the word lines are sequentially activated with a fixedcommon bit line.

In the above descriptions, one example of the word conditions is thatthe adjacent two of the word lines are sequentially activated with afixed common bit line. Notwithstanding, this case is not necessarily theworst case. For example, the worst case might be another case thatnon-adjacent two word liens are sequentially activated with a fixedcommon bit line. The worst case might be still another case that the bitlines are different and not common. Further, the tests not only underthe worst condition but also under other bad conditions might, in case,be needed. In accordance with the present invention, the refreshaddresses for the test operation are controllable in the tester side, sothat the test operation can surely be made under any conditions.

Further, in the embodiment, the description has been made in case thatthe test circuit is integrated in the semiconductor memory device. It ispossible, if necessary, that the test circuit and the semiconductormemory device are separated from each other but mounted on the samechip. In either structures, there is no problem, provided that the testcircuit and the semiconductor memory device are electrically coupled toeach other for transmitting signals and addresses between the testcircuit and the semiconductor memory device.

The present invention should not be limited to the structures of theabove described embodiment. A variety of modification to the embodimentmay be available unless the subject matter of the present invention ischanged.

EFFECT OF THE INVENTION

As described above, in accordance with the present invention, in thetest operation, the test-purpose refresh address is stored in theinternal data storage device, so that the test-purpose addressescorresponding to adjacent word lines to a word line designated by thetest-purpose refresh address are applied to the address terminal,whereby the read/write operation is made based on the test-purposeaddress and subsequently the refresh operation of the memory cell isconducted based on the test-purpose refresh address stored in the datastorage device.

Otherwise, the refresh operation of the memory cell is conducted beforethe read/write operation is made. Namely, the test may be conducted forany address combinations. This allows checking operations in the worstcase.

1. A test method for a semiconductor memory device with a plurality ofmemory cells which need, wherein during a test operation, there isaccomplished, at least one time, a combination of: a read/write processfor reading or writing a memory cell based on a first address externallyentered; and a refresh process for refreshing said memory cell based ona second address externally entered, and wherein said combination of twoprocesses is made in one cycle.
 2. The test method for a semiconductormemory device as claimed in claim 1, wherein said combination of twoprocesses is that after said refresh process is made, then saidread/write process is made.
 3. The test method for a semiconductormemory device as claimed in claim 1, wherein said combination of twoprocesses is that after said read/write process is made, then saidrefresh process is made.
 4. The test method as claimed in claim 1,further comprising: automatically performing self-refresh of the memorycell at a predetermined interval.
 5. The test method as claimed in claim1, wherein the semiconductor memory device is a pseudo SRAM.
 6. A testmethod for a semiconductor memory device with a plurality of memorycells which need refreshes, wherein during a test operation, there isaccomplished, at least one time, a combination of: a read/write processfor reading or writing a memory cell based on a first address externallyentered; and a refresh process for refreshing said memory cell based ona second address externally entered, and wherein said read/write processand said refresh process and further subsequent read/write process areaccomplished in one cycle.
 7. A test method for a semiconductor memorydevice with a plurality of memory cells which need refreshes, whereinduring a test operation, there is accomplished, at least one time, acombination of: a read/write process for reading or writing a memorycell based on a first address externally entered; and a refresh processfor refreshing said memory cell based on a second address externallyentered, and wherein said two processes are made at a common columnaddress and at row addresses close to each other.
 8. The test method fora semiconductor memory device as claimed in claim 7, wherein said twoprocesses are made at a common column address and at row addressesadjacent to each other.
 9. A test method for a semiconductor memorydevice with a plurality of memory cells which need refreshes, whereinduring a test operation, there is accomplished, at least one time, acombination of: a read/write process for reading or writing a memorycell based on a first address externally entered; and a refresh processfor refreshing said memory cell based on a second address externallyentered, and further including a process of discontinuing the refresh ofsaid memory cell based on a third address generated inside of saidsemiconductor memory device, in response to a switch of saidsemiconductor memory device from a normal operation mode to a test mode.10. The test method for a semiconductor memory device as claimed inclaim 9, wherein when a normal operation mode is switched to a test modebased on a mode switching signal externally entered, a test address isselected so that said refresh of said memory cell based on said thirdaddress is discontinued.
 11. A test method for a semiconductor memorydevice with a plurality of memory cells which need refreshes, whereinduring a test operation, there is accomplished, at least one time, acombination of: a read/write process for reading or writing a memorycell based on a first address externally entered; and a refresh processfor refreshing said memory cell based on a second address externallyentered, and wherein said test operation is that a set of plural rowaddresses is subject to said refresh process with fixing a columnaddress and sequentially changing row addresses.
 12. The test method fora semiconductor memory device as claimed in claim 11, wherein said testoperation is that a set of all row addresses is subject to said refreshprocess with fixing a column address and sequentially changing rowaddresses.
 13. The test method for a semiconductor memory device asclaimed in claim 11, wherein said test operation is that a set ofrespective all row addresses for each of plural blocks divided from amemory cell array is subject to said refresh process with fixing acolumn address and sequentially changing row addresses.
 14. A testmethod for a semiconductor memory device with a plurality of memorycells which need refreshes, wherein during a test operation, there isaccomplished, at least one time, a combination of: a read/write processfor reading or writing a memory cell based on a first address externallyentered; and a refresh process for refreshing said memory cell based ona second address externally entered, and wherein both said first addressand said second address are externally entered every changes of a rowaddress.
 15. A test method for a semiconductor memory device with aplurality of memory cells which need refreshes, wherein during a testoperation, there is accomplished, at least one time, a combination of: aread/write process for reading or writing a memory cell based on a firstaddress externally entered; and a refresh process for refreshing saidmemory cell based on a second address externally entered, and whereinsaid first address is externally entered every changes of the rowaddress, while only an initial address of said second address isexternally entered, and said second address is automatically changed inaccordance with a predetermined constant rule every changes to the rowaddress.
 16. The test method for a semiconductor memory device asclaimed in claim 15, wherein a predetermined increment of said secondaddress is made every changes to the row address.
 17. A test method fora semiconductor memory device with a plurality of memory cells whichneed refreshes, wherein during a test operation, there is accomplished,at least one time, a combination of: a read/write process for reading orwriting a memory cell based on a first address externally entered; and arefresh process for refreshing said memory cell based on a secondaddress externally entered, and wherein a hold test of a memory cell tobe subject to the test is previously tested and a predetermined testpattern is written, before said two processes are accomplished.
 18. Asemiconductor memory device having a plurality of memory cells whichneed refresh, a circuit element for supplying a first address, and anaccess address control circuit for refreshing a memory cell based on anaddress, wherein said semiconductor memory device further has: a circuitfor holding a second address externally entered; and a refresh addressswitching circuit electrically coupled to said circuit element forsupplying said first address and also coupled to said circuit forholding said second address, and in a normal operation mode, saidrefresh address switching circuit supplies said first address to saidaccess address control circuit, and in a test mode, said refresh addressswitching circuit supplies said second address to said access addresscontrol circuit.
 19. The semiconductor memory device as claimed in claim18, wherein said semiconductor memory device automatically performsself-refresh of the memory cell at a predetermined interval.
 20. Thesemiconductor memory device as claimed in claim 18, wherein saidsemiconductor memory device is a pseudo SRAM.
 21. The semiconductormemory device as claimed in claim 18, wherein said refresh addressswitching circuit comprises a selecting circuit which is electricallycoupled to said circuit element for supplying said first address andalso coupled to said circuit for holding said second address, and insaid normal operation mode, said selecting circuit selects said firstaddress, and in said test mode, said selecting circuit selects saidsecond address.
 22. The semiconductor memory device as claimed in claim21, wherein said selecting circuit comprises a multiplexer electricallycoupled to said circuit element for supplying said first address andalso coupled to said circuit for holding said second address.
 23. Thesemiconductor memory device as claimed in claim 18, further including: acontrol circuit electrically coupled to said refresh address switchingcircuit for supplying said refresh address switching circuit a controlsignal which switches between said normal operation mode and said testmode.
 24. The semiconductor memory device as claimed in claim 23,wherein said control circuit comprises a test entry circuit whichswitches between said normal operation mode and said test mode inresponse to a predetermined external signal.
 25. The semiconductormemory device as claimed in claim 18, wherein said circuit for holdingsaid second address comprises a data storage device electrically coupledto said refresh address switching circuit.
 26. The semiconductor memorydevice as claimed in claim 18, further including an address invertingcircuit electrically coupled to between said circuit for holding saidsecond address and said refresh address switching circuit for invertingsaid second address outputted from said circuit for holding said secondaddress, and supplying the same to said refresh address switchingcircuit.
 27. The semiconductor memory device as claimed in claim 18,wherein said circuit element for supplying said first address comprisesa refresh address generating circuit connected to said refresh addressswitching circuit.
 28. A test circuit for a semiconductor memory device,said circuit having a plurality of memory cells which need refresh and acircuit element for supplying a first address based on an internalsignal, wherein said test circuit has: a circuit for holding a secondaddress externally entered; and a refresh address switching circuitelectrically coupled to said circuit element for supplying said firstaddress and also coupled to said circuit for holding said secondaddress, and in a normal operation mode, said test circuit supplies saidfirst address to an access address control circuit, and in a test mode,said test circuit supplies said second address to said access addresscontrol circuit.
 29. The test circuit as claimed in claim 28, whereinsaid refresh address switching circuit comprises a selecting circuitwhich is electrically coupled to said circuit element for supplying saidfirst address and also coupled to said circuit for holding said secondaddress, and in said normal operation mode, said selecting circuitselects said first address, and in said test mode, said selectingcircuit selects said second address.
 30. The test circuit as claimed inclaim 29, wherein said selecting circuit comprises a multiplexerelectrically coupled to said circuit element for supplying said firstaddress and also coupled to said circuit for holding data.
 31. The testcircuit as claimed in claim 28, further including: a control circuitelectrically coupled to said refresh address switching circuit forsupplying said refresh address switching circuit a control signal whichswitches between said normal operation mode and said test mode.
 32. Thetest circuit as claimed in claim 31, wherein said control circuitcomprises a test entry circuit which switches between said normaloperation mode and said test mode in response to a predeterminedexternal signal.
 33. The test circuit as claimed in claim 28, whereinsaid circuit for holding said second address comprises a data storagedevice electrically coupled to said refresh address switching circuit.34. The test circuit as claimed in claim 28, further including anaddress inverting circuit electrically coupled to between said circuitfor holding said second address and said refresh address switchingcircuit for inverting said second address outputted from said circuitfor holding said second address, and supplying the same to said refreshaddress switching circuit.
 35. The test circuit as claimed in claim 28,wherein said test circuit is integrated in said semiconductor memorydevice.
 36. The test circuit as claimed in claim 28, wherein said testcircuit is separated from said semiconductor memory device and ismounted on a same chip as said semiconductor memory device.